This isn't much to look at, but it is vital to making any more progress. I now have interrupts turned on - the interrupt handler increments r9 and returns. You can see r9 is 1, then four interrupt/exceptions occur, then r9 is 5.
There were a lot of barriers to this:
- Several system tables had to be filled in: the IDT, TSS, and IOAPIC redirection table being the biggest ones (I am making things somewhat harder on myself by skipping the legacy interrupt mode). The TSS required another entry in the GDT. Also, I had to add a page table entry for the LAPIC, and set it up as well.
- I had to go through several rounds of IOAPIC settings. At first I was using lowest priority, logical, active high. Then I tried ExtInt. Finally, I figured out that I needed physical mode (the default LAPIC id is 0, which doesn't match any logical bit setting - I peeked at the Bochs LAPIC implementation!).
- I encountered a couple of triple faults. The first was due to trying to poke directly into upper memory region (mov [0xfee0_00f0], 0x100). The immediate value gets sign extended, and ends up off the end of virtual memory. Another was due to using segment selector "1" for my interrupt handler (because I want entry 1). Of course, the bottom three bits of the selector are shifted off, so I need "8".
- You can't just iret from a 64 bit interrupt handler. For some reason, you have to hard code in the word size override ("db 0x48; iret").
1 comment:
I figured out the iret thing. You need iretq
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